RGF's Client - Japanese tech company - is looking for Design & Verification Engineer to perform comprehensive front-end design verification for ASIC and LSI products, ensuring functional correctness and quality from customer specifications through RTL design and advanced verification methodologies.

• Working Location: Thanh My Tay Ward, HCMC
• Monthly Salary: 25,000,000 ～ 35,000,000VND (Gross)
• Job Responsibilities:
  - Analyze customer requirements and specifications to define verification scope.
  - Develop and document functional specifications and implementation specifications.
  - Create RTL code using Verilog / SystemVerilog.
  - Formulate and document the overall verification strategy and detailed verification item tables.
  - Design and build verification environments and scenarios using SystemVerilog, SVA, UVM, and C.
  - Write and maintain verification environment manuals.
  - Execute verification plans, analyze results, and compile verification reports.
  - Perform front-end design and verification of ASICs (Application-Specific Integrated Circuits).
  - Conduct design and verification using general-purpose bus protocols such as AMBA (AXI/AHB/APB).
  - Implement Assertion-Based Verification methodologies.
  - Undertake verification tasks for designs involving built-in CPUs.
  - Verify high-speed interfaces like PCI Express and USB.
  - Implement random verification techniques using SystemVerilog.
  - Complete other technical or project-related tasks assigned by the manager.
  

Necessary Skill / Experience:

• Language: English at an intermediate level.
• Experience: More than 2 or 3 years of experience as an engineering leader in the semiconductor industry.
• Skills in front-end design and verification of ASICs.
• Skills in RTL design using Verilog HDL/VHDL.
• Skills in design and verification using the general-purpose bus AMBA (AXI/AHB/APB).
• Skills in Assertion-Based Verification.
• Must be a technician who can perform tasks independently.

Preferable Skill/ Experience:

• English skill at Business level for overseas business trips and meetings with overseas engineers.
• Experience in design and verification of ASIC with built-in CPU.
• Experience in design and verification of high-speed interfaces such as PCI Express and USB.
• Experience with random verification using SystemVerilog.
• Experience in testbench building applying verification methodology (UVM).

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